The present invention relates to fabricating methods for semiconductor packages, and more particularly, to a fabricating method for a semiconductor package, in which a semiconductor chip has a surface exposed to outside of the semiconductor package so as to improve heat dissipating efficiency.
In a semiconductor package, much attention and effort have been directed to effective dissipation of heat generated by a semiconductor chip for assuring the lifetime and quality of the chip.
As an encapsulant for encapsulating the chip is formed of a molding compound such as epoxy resin poor in thermal conductivity, the heat generated by the chip can not be effectively dissipated through the encapsulant. In this case, a heat sink is incorporated in the semiconductor package, wherein the heat sink is made of a metal good in thermal conductivity, in an effort to improve heat dissipating efficiency. However, if the heat sink is entirely embedded in the encapsulant, the heat needs to pass through the encapsulant for dissipation, which therefore restricts the improvement in the heat dissipating efficiency. Therefore, it is desired to construct the semiconductor package in a manner that the chip has a surface exposed to outside of the semiconductor package, so as to allow the heat to be dissipated directly through the exposed surface to the atmosphere.
Accordingly, U.S. Pat. No. 5,450,283 discloses a semiconductor package illustrated in FIG. 5. In the semiconductor package 10, a semiconductor chip 18 has a top surface 22 exposed to outside of an encapsulant 40, for allowing heat generated by the chip 18 to be dissipated directly to the atmosphere without passing through the encapsulant 40. This makes the semiconductor package 10 more improved in heat dissipating efficiency than the foregoing semiconductor package.
However, several drawbacks have been found in the fabrication of the semiconductor package 10. First, as shown in FIG. 6, in a molding process for forming the encapsulant 40 by a molding compound, prior to placing the chip 18 associated with a substrate 12 in a molding cavity 30 of a mold, a tape 38 is attached to a top wall of the molding cavity 30, so as to make the top surface 22 of the chip 18 closely abut the top wall of the molding cavity 30 through the tape 38 after an upper mold is engaged with a lower mold of the mold, and to prevent the molding compound from flashing on the top surface 22 of the chip 18. Nevertheless, if the substrate 12 having the chip 18 mounted thereon is overall not sufficiently high, and the top surface 22 of the chip 18 can not closely abut the top wall of the molding cavity 30, a gap is then formed between the chip 18 and the molding cavity 30, and makes the molding compound for forming the encapsulant 40 flash on the top surface 22 of the chip 18. In this case, the semiconductor package 10 can be undesirably affected in heat dissipating efficiency and in profile by the flash of the molding compound on the top surface 22 of the chip 18, and thus a deflash process is required. However, the deflash process is disadvantageous in time-consuming, increasing the fabrication cost and damaging the semiconductor package. Alternatively, if the substrate 12 accommodating the chip 18 overall is excessively high, the chip 18 then abuts the top wall of the mold cavity 30 with such a great force as to make the chip 18 crack.
Moreover, the tape 38 attached to the top wall of the molding cavity 30 is generally made of an expensive heat-resistant material to be remained intact at a high temperature in the molding process, and thus the fabrication cost can not be reduced. Further, the tape 38 is necessarily disposed on the top wall of each molding cavity 30 in a precise and flat manner, this increases the complexity and time expense for the fabrication process, and thus is disadvantageous for reducing the fabrication cost and improving the production efficiency. In addition, the engagement of the upper mold with the lower mold generates a stress, which is transmitted through the tape 38 to the chip 18 and causes cracking damage to the chip 18, so that the semiconductor package can not be improved in quality and the fabrication cost is hard to be reduced.
Furthermore, in the molding process, the mold employed in the semiconductor package 10 is constructed corresponding in dimension to the package to be fabricated. This therefore increases the fabrication cost and time expense, and reduces the fabrication efficiency.
A primary objective of the present invention is to provide a fabricating method for a semiconductor package, in which heat generated by a semiconductor chip can be dissipated through an exposed surface of the chip to the atmosphere and flash of a molding compound can be prevented from occurrence, so as to improve heat dissipating efficiency. Further, the fabricating method for a semiconductor package prevents the chip from being damaged in a molding process, and thus assures the quality of the semiconductor package. Moreover, it is not necessary to attach a tape on a top wall of a molding cavity in the molding process, which simplifies the fabricating method and reduces fabrication cost and time expense. Furthermore, in the fabricating method, attachment of the chip to a substrate is not precisely controlled in height, and thus the fabrication cost is reduced and production rate is improved. In addition, a mold used in the fabricating method can be employed for fabricating semiconductor packages various in dimension, so that the fabrication cost is reduced.
In accordance with the foregoing and other objectives, the present invention proposes a fabricating method for a semiconductor package, comprising the steps of:
preparing a chip carrier such as a matrix type substrate module plate, which is consisting of a plurality of substrates;
mounting at least one semiconductor chip on each of the substrates in a manner that a first surface of the chip is attached to a predetermined position on a second surface of the substrate;
preparing a covering module plate consisting of a plurality of covering plates and sufficiently dimensioned for entirely covering all the substrates, and forming an interface layer on a first surface of the covering module plate, wherein the interface layer is poor in adhesion to the chip and a molding compound used for forming an encapsulant, and has the adhesion to the chip and the molding compound smaller than that to the covering module plate;
attaching the interface layer on the covering module plate to all the chips, in a manner that the interface layer formed on a first surface of each of the covering plates is disposed on a second surface opposing the first surface of the chip;
performing a molding process;
performing a ball implantation process;
performing a singulation process; and
heating a singulated semi-fabricated semiconductor package, so as to allow the interface layer to be delaminated from the chip and a portion of an encapsulant formed around the chip, according to a difference in coefficient of thermal expansion between the interface layer and the chip, and the interface layer and the molding compound of the encapsulant. This makes the interface layer, the covering plate and a portion of the encapsulant formed on a second surface of the covering plate easily removed from the second surface of the chip and the portion of the encapsulant formed around the chip.
Combined structure of the covering module plate and the chips is lower in height than a molding cavity of a mold used in the molding process, that is, the molding compound encapsulates the second surface of the covering module plate during molding. However, the interface layer, the covering plate and the molding compound formed on the second surface of the covering plate can be easily removed by heating the singulated seim-fabricated semiconductor package, since the interface layer has adhesion to the chip and the molding compound smaller than that to the covering module plate.
Moreover, an exposed surface of the chip does not abut a top wall of the molding cavity, so that it is not necessary to dispose a tape on the top wall, and thus the fabricating method can be simplified and the chip can be prevented from being damaged during molding.
Furthermore, due to flexibility in height for combined structure of the covering module plate, the chips and the substrate module plate, and also due to free adjustment in quantity and arrangement for the substrates on the chip carrier corresponding in dimension to chips or semiconductor packages, the mold used in the molding process can be employed for fabricating the semiconductor packages various in dimension.
The covering module plate is made of a metallic material such as copper, aluminum, copper alloy or aluminum alloy, or a substrate consisting of a tape or BT (bismaleimide triazine) resin having surfaces thereof each covered with a foil or layer formed of a metallic material such as copper, aluminum, copper alloy or aluminum alloy. The interface layer on the covering module plate is made of an adhesive poor in adhesion to the chips and the molding compound, epoxy resin, a metallic material such as gold, chromium, nickel or alloy thereof, or Teflon, so as to allow the interface layer have the adhesion to the molding compound and the chips smaller than that to the covering module plate. In this case, the interface layer, the covering plate and the molding compound formed on the second surface of the covering plate can be easily removed from the second surface of the chip and the portion of the encapsulant formed around the chip.
In a preferred embodiment of the invention, the chip carrier consists of at least one BGA (ball grid array) substrate, while the substrate is formed with a hole for allowing bonding wires to pass therethrough and to electrically connect the substrate to a semiconductor chip. On a first surface of the substrate there are implanted a plurality of solder balls for electrically connecting the chip to external devices.
In another preferred embodiment of the invention, the chip carrier consists of at least one flip-chip substrate, that is, a second surface of the substrate has a plurality of array-arranged bumps pads, which are used to bond a plurality of solder bumps thereon for electrically connecting a semiconductor chip to the substrate through the solder bumps. Moreover, a first surface of the substrate is implanted with a plurality of solder balls for electrically connecting the chip to external devices.
In addition, in order to enhance the adhesion of the chip to the encapsulant, side surfaces of the chip can be roughed, corrugated or made uneven by using a conventional process.